Analog / Mixed Signal IC Designer

Mao-Cheng Lee

Mao-Cheng Lee

About

Mao-Cheng Lee received the B.S and M.S degree from National Chiao Tung University, Hsinchu, Taiwan, in 2011 and 2013, respectively. He is currently working toward the M.S degree in electrical engineering and computer science at the University of California, Irvine, CA, USA. Mr. Lee is the recipient of 2015 Fellowship Award winner of University of California Irvine, Department of Electrical Engineering and Computer Science. His research interests include mixed-signal and low power integrated circuit design.

From 2013 to 2015 he was with Airoha Technology Corp. (Mediatek Subsidiary), Taiwan, where he was involved in the design of frequency synthesizers and calibration systems for Wi-Fi, satellite tuner and Bluetooth products. He is currently working at Ethertronics Inc. Irvine, CA which He is working of mixed signal/analog circuit design.

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Resume

  • 2007-2011

    B.S. National Chiao Tung University, (Hsinchu, Taiwan)

    Electrical and Computer Engineering
  • 2011-2013

    M.S. National Chiao Tung University, (Hsinchu, Taiwan)

    Electrical and Electronics Engineering
    • Master Thesis: Design of Low Power Successive Approximation Register Analog-to-Digital Converter
      • Implemented a 12-bit successive approximation analog-to-digital converter with digital calibration circuit using TSMC 40nm and 65nm CMOS technology. (Including chip tape-out and measurement)
      • Implemented 10-bit successive approximation analog-to-digital converter using resistor-based DAC in TSMC 65nm CMOS technology. (In cooperation with Taiwan’s National Applied Research Laboratories.) (Including chip tape-out and measurement)
      • Implemented a 12-bit pipelined analog-to-digital converter in TSMC 0.18um CMOS technology.
  • 2013-2015

    AIROHA Technology Corp. (MediaTek Inc. subsidiary), (Hsinchu, Taiwan)

    Analog IC Design Engineer
    • Designed low phase noise synthesizers for Wi-Fi and satellite tuner products.
    • Designed BT4.0 (BLE) low power synthesizers in 55nm CMOS technology. (for sigma delta direct modulation)
    • Modified VCO bank and synthesizer calibration circuits.
    • Compile a Perl program for parasitic capacitor cancellation to reduce the LO leakage to be below -100dBm.
  • Sep.2015-Apr.2018

    M.S. University of California, Irvine, (Irvine, CA)

    Electrical Engineering and Computer Science; Advisor: Prof. Payam Heydari
    • Designed and measured ultra-low-power (RX: 42uW with -79dB sensitivity) wireless transceivers for brain-computer interface application.
    • Implemented and measured all-digital RX offset and LO frequency-drift calibration circuits.
    • Designed and measured MedRadio Band PCB antenna.
    • Adaptive high-voltage stimulator system design with charge-balancing calibration.
    • Switched-capacitor charge pump DC-DC (5~30V) converter design.
  • Apr.2018-Dev.2018

    Ethertronics. (Irvine, CA)

    Analog/RF IC Design Intern
    • Designed PMU block (including bandgap, LDO, PTAT)
    • Implemented power detector for Wifi PA (5.5 GHz)
  • Jan.2019-Present

    Analog Bits

    Senior Mixed Signal IC Design Engineer
    • Designed high-speed SerDes blocks in 8/7nm CMOS process, including multi-stages continuous-time linear equalizer (CTLE), VGA, quadrature divider and de-serializer. (for 32/16Gb/s PCIE 5/4/3 standard)
    • Developed a fast PLL/reference clock system phase noise and jitter modeling/simulation method from scratch (open/close loop) for synthesizer/SerDes system design and verification.
    • Supervised/guided/debug high-speed analog layout (including EM-IR) in deep sub-micron process.

Honors

Skills

SpectreRF
Cadence Virtuoso
Hspice
Verilog-A
Altium
HFSS
Ocean
Matlab
Perl
C/C++
EMX
ADS

Works

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SAR ADC

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Low Phase Noise BLE PLL

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Ultra-Low Power Transceiver

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Brain Stimulator

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DC-DC Converter

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Semiconductor Laser

Habits

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Baseball

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Photography

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Workout

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Dog

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Coffee

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